In Fall 2027, I will join the Department of Computer Science at the University of California, Irvine, as an Assistant Professor. Before that, I will spend a year as a Visiting Faculty Researcher at Google in Sunnyvale. I am recruiting multiple PhD students to join my group at UCI. If you are interested, please feel free to send me an email!

Although my research primarily focuses on computer architecture, I would also be excited to hear from students interested in applied machine learning for systems, networking, emerging device technologies, or heterogeneous integration.

Hi! I am Gerasimos Gerogiannis, a Visiting Faculty Researcher at Google and an incoming Assistant Professor of Computer Science at the University of California, Irvine. Since Gerasimos can be difficult to pronounce, I usually go by my nickname, Makis.

I received my PhD from the University of Illinois Urbana-Champaign (UIUC), where I was a member of the i-acoma group and was fortunate to be advised by Professor Josep Torrellas. Before joining UIUC, I earned a Diploma in Electrical and Computer Engineering (equivalent to a combined BSc and MSc) from the University of Patras in Greece.

I am interested in building efficient accelerator-based heterogeneous systems for machine learning and scientific applications. My research has exposed fundamental barriers to the efficiency of modern specialization-rich systems, stemming from legacy general-purpose design practices. To overcome such barriers, I have re-architected and co-designed the end-to-end system stack around heterogeneity – from accelerators to processors, networks, algorithms, and optimizing compilers. I refer to this holistic system design paradigm as accelerator-centric.

To bridge the gaps between hosts and devices, I have co-designed processor and accelerator architectures that eliminate control and data movement overheads [SPADE-ISCA’23],[DECA-MICRO’25,[ATX-ISCA’26]. Further, I have proposed both analytical and machine learning-aided methods that automate performance optimization, making emerging accelerators easier to program and tune [Bandit-MICRO’23],[HotTiles-HPCA’24],[COGNATE-ICML’25],[Micro-Mama-MICRO’25]. Finally, I redesigned software communication algorithms and hardware networking devices to make distributed heterogeneous systems easier to scale [Two-Face-ASPLOS’24],[MeshSlice-ISCA’25],[NetSparse-MICRO’25].

Beyond accelerator-centric system design, I am broadly interested in applications of machine learning to computer systems and architecture.

My work has appeared in leading computer architecture and machine learning venues, including ISCA, MICRO, ASPLOS, HPCA, and ICML. I have also filed four U.S. patents with Intel on redesigning CPU architectures for machine learning workloads. My research has been recognized with one IEEE MICRO Top Pick and one Honorable Mention.